Low supply voltage analog multiplier

ABSTRACT

The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells, each cell comprising a pair of bipolar transistors with coupled emitters. A first transistor of each cell receives an input signal on its base terminal and has its collector terminal coupled to a first voltage reference through a bias member. Advantageously, the second transistor of each cell is a diode configuration, and the cells are interconnected at a common node corresponding to the base terminals of the second transistors in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

TECHNICAL FIELD

[0001] This invention relates to an improved analog multiplier, whereinenhanced accuracy at low supply voltages is achieved for but a minimalincrease in circuit area.

[0002] More particularly, the invention relates to a low supply voltageanalog multiplier which comprises a pair of differential cells, witheach cell being comprised of a pair of bipolar transistors with coupledemitters, a first transistor of each cell receiving an input signal onits base terminal and having its collector terminal coupled to a firstvoltage reference through a bias member.

BACKGROUND OF THE INVENTION

[0003] The processing of analog signals often requires circuits whichcan output a proportional signal to the product of two analog inputsignals.

[0004] Such circuits are commonly termed analog multipliers. Forexample, analog multipliers are used for balancing modulators, as wellas in phase detectors and the like devices. With digital signalconverters having a quadratic type of transfer function, it is essentialthat an analog multiplier be employed to produce a proportional signalto two analog input signals which are identical with each other.

[0005] A large number of analog multipliers are based on an exponentialtransfer function of bipolar transistors (BJTs). Actually, adifferential stage with coupled emitters may constitute an elementarymultiplier cell capable of generating (differential) collector outputcurrents which are dependent on a differential voltage applied to itsinputs, e.g., to the base terminals of a bipolar transistor pair formingthe differential stage.

[0006] By duplicating an elementary cell, analog multipliers can beobtained which can operate between two or among four quadrants of adifferential plane of input voltages.

[0007] A typical cell of a four-quadrant multiplier is referred to inthe literature as Gilbert's cell or circuit.

[0008] A reference for this circuit structure is, for example, IEEEJournal of Solid-State Circuits, vol. sc-19, No. 6, December 1974, NewYork, U.S.A., pages 364-373, Berrie Gilbert “A High-PerformanceMonolithic Multiplier Using Active Feedback.”

[0009] In multipliers of this kind, an expedient is often resorted to inorder to reduce the error introduced by non-linearities of the circuit.Briefly, a pre-distortion stage is connected in, upstream of the analogmultiplier, to introduce pre-distortion in the input signal andcompensate for the hyperbolic tangent transfer characteristic of themultiplier cell.

[0010] The pre-distortion stage is usually in the form of adiode-configured bipolar transistor whereby a current input signal isforced to produce a voltage output signal having a transfer functionwhich is the reciprocal of the hyperbolic tangent.

[0011] Multipliers of this type are known in the literature, e.g., froma book “Analog Integrated Circuits—Analysis and Design” by Paul R. Greyand Robert G. Meyer, McGraw-Hill, which contains a detailed descriptionand an analysis of these circuits under Chapter 10, pages 694-705.

[0012] The basic characteristics expected of an analog multipliersinclude: high accuracy, relatively low power consumption, and moderatecircuit complexity.

[0013] However, obtaining one of these characteristics sometimesinvolves the need for a trade-in with one or all of the othercharacteristics.

[0014] In particular, the prior analog multipliers mentioned abovecannot be implemented with low supply voltages.

[0015] Also, the common mode output voltage varies as the potential at acentral node of the multiplier, which potential is equal to the half sumof the inputs, and this makes conventional multipliers too readilyaffected by sharp variations in the input signal.

[0016] Finally, the accuracy of DC gain is dependent on the value of Iof the bias generators.

SUMMARY OF THE INVENTION

[0017] An embodiment of this invention provides an analog multiplierstructure of uniquely simple constructional and functional features,which can be supplied a very low supply voltage and allows a pluralityof stages to be cascade connected to enhance input linearity whileretaining a fair speed, thereby overcoming the limitations of priorsolutions. The analog multiplier is highly reliable in operation andcomparatively inexpensive to manufacture.

[0018] The multiplier is one in which the dynamic of the signal at theheads of the compressor and of the expander is constant regardless ofthe multiplier value of gain. This ensures a multiplier harmonicdistortion which is constant and independent of the multiply factor ofthe stage. The analog multiplier includes a plurality of cells each withsecond transistor in a diode configuration. The cells are interconnectedat a common node corresponding to the base terminals of the secondtransistors in each pair.

[0019] The features and advantages of a multiplier according to theinvention will be apparent from the following description of anembodiment thereof, given by way of non-limitative example withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In the drawings:

[0021]FIG. 1 shows schematically an analog multiplier according to theprior art;

[0022]FIG. 2 shows schematically an analog multiplier according to theinvention; and

[0023]FIG. 3 is a more detailed view of a set of cascade-connectedmultipliers according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0024] With reference to the drawings, in particular to FIG. 2 thereof,the circuit structure of an analog multiplier embodying this inventionand preferably intended for use in signal modulators, is shown generallyat 1 in schematic form.

[0025] The structure 1 includes a first circuit portion 10 and a secondcircuit portion 11 connected to each other. These portions 10, 11 areessentially differential cells interconnected into a fully differentialconfiguration.

[0026] The first portion or cell 10 comprises a first bipolar transistor2 which has a control terminal, being its base terminal, arranged toreceive a first input signal Vin+.

[0027] The first transistor 2 has a conduction terminal, being itscollector terminal, connected to a first supply voltage reference Vccthrough a diode 4 which is forward biased to the power supply.

[0028] The collector node forms a first output terminal OUT− of themultiplier 1.

[0029] The portion 10 further comprises a second bipolar transistor 3having its emitter terminal connected to the emitter terminal of thefirst transistor 2.

[0030] The emitter terminals of the first 2 and the second 3 transistorsare connected to a second voltage reference GND through a currentgenerator 5 which is to deliver a current 2I.

[0031] The base and collector terminals of the second transistor 3 areinterconnected, thus providing a diode configuration of the transistor.

[0032] The base terminal of the second transistor 3 also forms a node Aof interconnection for the first 10 and the second 11 cells of thecircuit structure 1.

[0033] The second cell 11 is similar to the first and connected to thefirst cell 10 in mirror-image relationship. The second cell 11 alsocomprises a first bipolar transistor 6 having a base terminal arrangedto receive a second input signal Vin−.

[0034] The first transistor 6 of the second cell 11 has a collectorterminal connected to the first supply voltage reference Vcc through adiode 8 which is forward biased to the power supply.

[0035] The collector node forms a second output terminal OUT+ of themultiplier 1.

[0036] The second cell 11 further comprises a second bipolar transistor7 having its emitter terminal connected to the emitter terminal of thefirst transistor 6.

[0037] The emitter terminals of the first 6 and the second 7 transistorsof the second cell 11 are connected to the second voltage reference GNDthrough a current generator 9 which is to deliver a current 2I.

[0038] The base and collector terminals of the second transistor 7 areinterconnected, thus providing a diode configuration of the transistor.

[0039] Advantageously, a current generator 12, delivering a current 2Ito the node A, is connected between the node A interconnecting the cells10, 11 and the first voltage reference Vcc.

[0040] The transistors of the structure 1 are all npn bipolartransistors. However, the circuit could be arranged to comprise pnptransistors instead.

[0041] In an alternative embodiment, moreover, the second transistor 7of the second cell 11 may be slightly larger than the second transistor3 of the first cell 10, e.g., to a dimensional ratio of 1.8.

[0042] By changing the value of the current I of the generators 5, 9 and12, the transconductance value of the transistors 3 and 7 can be made tochange, thus varying the gain value of the multiplier.

[0043] Unlike prior solutions, the multiplier 1 has a DC output voltageVout which remains fixed as the current I of the bias generators varies,this being an optimum condition for a minimal harmonic distortion.

[0044] As shown in FIG. 3, the multiplier 1 is suitable for connectionin cascade with other multipliers of the same type; in this way, inputlinearity is enhanced. The load diodes 4, 8 would then be connected tothe first cell and the last cell in the cascade.

[0045] The multiplier 1 provides a structure of uniquely simpleconstructional and functional features, and offers a number ofadvantages, foremost among which is that the multiplier can be suppliedvery low voltages, below 3 V.

[0046] The common mode voltage is the difference in base-emitter voltagedrop between the transistors 2 and 3 of FIG. 2.

[0047] The circuit structure 1 is quite simple, and has shown to beextremely fast.

[0048] Changes and modifications may be made unto the structuredescribed hereinabove, within the scope of the invention as defined inthe accompanying claims.

1. A low supply voltage analog multiplier, comprising a pair ofdifferential cells, with each cell being comprised of a pair of bipolartransistors with coupled emitters, a first transistor of each cellreceiving an input signal on its base terminal and having its collectorterminal coupled to a first voltage reference through a bias member, thesecond transistor of each cell having a diode configuration, and thecells being interconnected at a common node corresponding to baseterminals of the second transistors in each pair.
 2. A multiplieraccording to claim 1 , further comprising a first current generatorconnected between said first voltage reference and said common node. 3.A multiplier according to claim 2 , further comprising a second currentgenerator connected between the coupled emitters of the first cell and asecond voltage reference; and a third current generator connectedbetween the coupled emitters of the second cell and the second voltagereference, the second and third current generators each being structuredto deliver a current equal to a current from said first currentgenerator connected to said common node.
 4. A multiplier according toclaim 1 , wherein the collector terminals of the first transistors ineach pair form differential outputs of the multiplier.
 5. A multiplieraccording to claim 1 , having a fully differential configuration.
 6. Amultiplier according to claim 1 , wherein all the transistors are npnbipolar transistors.
 7. A multiplier according to claim 1 , said biasmember comprises a diode which is forward biased to the first supplyvoltage reference.
 8. A multiplier according to claim 1 , wherein thesecond transistor of the second cell exceeds in area the secondtransistor of the first cell.